The present application relates to a stacked nanosheet semiconductor structure and a method of forming the same. More particularly, the present application relates to a gate-all-around structure in which strain has been introduced into a vertical stack of semiconductor channel material nanosheets after the semiconductor channel material nanosheets have been suspended.
Gate-all-around nanosheet structures containing a plurality of vertically stacked and suspended semiconductor channel material nanosheets are a good candidate for the replacement of FinFET structures at the 5 nm technology node and beyond. Such gate-all-around nanosheet structures offer increased effective width (Weff) per active footprint and better performance compared to finFETs. In gate-all-around nanosheet structures containing a plurality of vertically stacked and suspended semiconductor channel material nanosheets, the stacked nanosheet formation relies on the selective removal of one semiconductor material (i.e., the sacrificial semiconductor material nanosheet) relative to another semiconductor material (i.e., the semiconductor channel material nanosheet) to form vertically stacked and suspended semiconductor channel material nanosheets for gate-all-around devices.
It is known that channel strain is relaxed after removing the sacrificial semiconductor material nanosheets and thus suspending the semiconductor channel material nanosheets. It is difficult to apply external strain afterwards, and there is no known process that aims to enhance the performance of the nanosheet transistor via channel stain. Thus, there is a need for providing a method to apply stain after the formation of suspended semiconductor channel material nanosheets.